Semiconductor device fabrication of today frequently involves forming of various patterns, such as lines or trenches in a layer, for instance in a hard mask layer, a dielectric layer, a metal layer or a semiconductor layer.
In lithographically based patterning techniques (i.e. “litho-etch”), a photoresist layer may be formed above the layer which is to be patterned. The photoresist layer may be lithographically patterned (i.e. exposed and developed) and the pattern in the photoresist layer may then be transferred into the underlying layer by etching while using the patterned photoresist layer as an etch mask. Lithographically based patterning techniques may also involve transferring the pattern in the photoresist layer into a mask layer (typically a hard mask layer) in one or more etching steps, and thereafter using the mask layer in a final pattern transfer step into an underlying layer.
In spacer-assisted multiple patterning techniques (also known as self-aligned multiple patterning techniques) such as SADP or SAQP, grating-like patterning layers of mandrel lines and spacer lines may be used to form tight pitch line patterns in an underlying layer. Multiple patterning may be combined with block techniques to enable forming of interrupted or discontinuous lines.
The minimum critical dimensions (CDs) of litho-etch based patterning is limited by among others the wavelength of the light used for exposing photoresist. Although extreme ultraviolet lithography (EUVL) enables forming patterns with reduced CDs compared to current technologies based on for instance 193i, edge placement errors (EPE) still imposes a limit on the minimum attainable CD. Meanwhile, SADP and SAQP enables forming of comparably tighter pitch patterns. However, while lithographically based patterning techniques allows forming of patterns of various shapes, self-aligned multiple patterning techniques are typically limited to forming regular and repeating line-based patterns.